High density mos technology power device

ABSTRACT

A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window. The second insulating material layer includes a second elongated window extending above each elongated body region. The second insulating material layer seals the edges of the conductive material layer from a source metal layer disposed over the second insulating material layer. The source metal layer contacts each body region and each source region through each second elongated window along the length of the elongated body region.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of application Ser. No.08/960,561, filed Oct. 29, 1997, which in turn is a division ofapplication Ser. No. 08/738,584, filed Oct. 29, 1996, entitled HIGHDENSITY MOS TECHNOLOGY POWER DEVICE, which prior applications areincorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to either discrete devices orintegrated power semiconductor devices including MOS-gated power devicessuch as, for example, power MOSFETS, IGBTs, MOS-gated thyristors orother MOS-gated power devices. In particular, the invention relates to aMOS-gated power device having a smaller minimum dimension Lp that yieldsan increased density of MOS-gated power devices per unit area.

[0004] 2. Discussion Of The Related Art

[0005] MOS technology power devices as known in the related art arecomposed of a plurality of elementary functional units integrated in asemiconductor chip. Each elementary functional unit is a verticalMOSFET, and all the elementary functional units are connected inparallel. With this arrangement, each elementary vertical MOSFETcontributes a fraction of an overall current capacity of the powerdevice.

[0006] A MOS technology power device chip typically includes a lightlydoped semiconductor layer of a first conductivity type forming a commondrain layer for all the elementary vertical MOSFETS. The lightly dopedlayer is superimposed over a heavily doped semiconductor substrate. Eachelementary functional unit includes a body region of a secondconductivity type formed in the common drain layer. U.S. Pat. No.4,593,302 (Lidow et al.) discloses a so called “cellular” power device,wherein the body region of the elementary functional units has apolygonal layout, such as for example a square or hexagonal shape. Forthis reason, the elementary functional units are also called “elementarycells”. In addition, MOS technology power devices are also known in therelated art wherein the body region of each elementary functional unitsis an elongated stripe.

[0007] For any of the above power MOS devices, a typical verticalstructure of the elementary functional units (i.e. a cross-section view)of the MOS technology power device is as shown in FIG. 1. In FIG. 1, theheavily doped semiconductor substrate is indicated by reference numeral1 and the lightly doped semiconductor layer is indicated by referencenumeral 2. The body region 3 of the elementary functional unit includesa central heavily doped portion 4, called a “deep body region”, and alateral lightly doped portion 5, having a lower dopant concentrationthan the heavily doped deep body region, which forms a channel region ofthe elementary vertical MOSFET. A doping level of the lateral portions 5of the body region determines a threshold voltage of the power device.Inside the body region 3, a source region 6 of the same conductivitytype as the common drain layer 2 is formed. A thin oxide layer 7 (a gateoxide layer) and a polysilicon layer 8 (a gate electrode of the powerdevice) cover a surface of the semiconductor layer 2 between the bodyregions 3, and the layers also extend over the lightly doped lateralportion of the body regions. The polysilicon layer 8 is covered by adielectric layer 9 in which contact windows 11 are opened over each bodyregion to allow a superimposed metal layer 10 (a source electrode of thepower device) to be deposited through the contact window and to contactthe source regions 6 and the deep body region 4.

[0008] In the structure of FIG. 1, a short-circuit is defined betweenthe source region and the deep body region to prevent a parasiticbipolar junction transistor having an emitter, a base and a collectorrespectively formed by the source region 6, the deep body region 4 andthe heavily doped semiconductor substrate 1, from triggering on. Theparasitic bipolar transistor will trigger “on” if the lateral currentflow in the body below the source produces a voltage drop greater thanapproximately 0.7V, forward biasing the emitter-to-base (EB) junction.The deep body region 4 increases the ruggedness of the power devicebecause it reduces the base resistance of such a parasitic transistor.

[0009] The structure of FIG. 1 is manufactured by forming the commondrain layer 2 over the heavily doped substrate 1, generally by means ofan epitaxial growth. The thin oxide layer 7 is thermally grown over anactive area of the common drain layer 2, wherein the elementaryfunctional units of the MOS-gated power device will be formed, and thepolysilicon layer 8 is deposited on the thin oxide layer. The deep bodyregions 4 are formed by selective introduction via a mask of a high doseof a dopant to form the central heavily doped deep body regions 4.Windows 12 are formed in the gate oxide layer and the polysilicon layerby a selective etching of the polysilicon and gate oxide layers via asecond mask to open the windows 12 where the elementary functional unitswill be formed. The lateral lightly doped portions of the body regionsare then formed by selective introduction of a low dose of dopants intothe common drain layer through the windows to form the lightly dopedportions of the body regions. Next, the source regions 6 are formed aswill be described in more detail below, followed by deposition of thedielectric layer 9 and selective etching thereof to open the contactwindows 11. The metal layer 10 is then deposited and patterned.

[0010] This process involves the use of a minimum of fourphotolithographic masks: a first mask is used for the formation of thedeep body regions 4; a second mask is used to selectively etch thepolysilicon 8 and gate oxide 7 layers; a third mask is used to form thesource regions 6 and a fourth mask is used to open the contact windows11 in the dielectric layer 9. The mask for the introduction of thedopants forming the source regions is provided partially by thepolysilicon and oxide layers, and partially by photoresist isles over amiddle portion of the deep body regions 4. The photoresist isles areformed by depositing a photoresist layer over the common drain layer,selectively exposing the photoresist layer to a light source, andselectively removing the photoresist layer to provide the photoresistisles.

[0011] Referring again to FIG. 1, a dimension Lp of each window 12 inthe polysilicon 8 and gate oxide 7 layers is given by equation (1):

Lp=a+2t  (1)

[0012] where “a” is the width of the contact window 11 in the dielectriclayer 9 and “t” is the distance between an edge of the polysilicon 8 andgate oxide 7 layers and an edge of the window 11 in the dielectric layer9. The dimension “a” of the contact window is given by equation (2):

a=c+2b  (2)

[0013] where “b” is a distance between an edge of the contact window 11and an inner edge of the source region 6, or in other words the lengthof the source region available to be contacted by the metal layer 11,and “c” is the dimension of a surface of the deep body region whereinthe source regions are absent or in other words the distance between theinner edges of the source regions, corresponding to the length of thesurface of the deep body region available to be contacted by the metallayer. The dimension Lp is therefore given by equation (3):

Lp=c+2b+2t  (3)

[0014] Accordingly, the elementary functional units of the related arthave the dimension Lp determined by “three feature sizes”, in particularthe dimension Lp depends on the parameters “c”, “b” and “t”.

[0015] In MOS technology power devices, the electrical parameters to beoptimized are the output resistance in the “on” condition Ron, agate-to-drain capacitance (feedback capacitance) and a gate-to-sourcecapacitance (input capacitance) of the MOS technology power device for aspecific die size and breakdown voltage. The output resistance Ron isthe sum of several components, each of which is associated with aparticular physical region of the device. More specifically, Ron is madeup of the components as shown in equation (4):

Ron=Rc+Racc+Rjfet+Repi  (4)

[0016] where Rc is a channel resistance associated with the channelregion, Racc is an accumulation region resistance associated with asurface portion of the common drain layer between the body regions,Rjfet is a resistance associated with a portion of the common drainlayer between depletion regions of the body regions 5, and Repi is aresistance associated with a portion of the drain layer beneath the bodyregions.

[0017] The channel resistance Rc depends on process parameters such asthe dopant concentration of the channel region. In other words Rc isproportional to the threshold voltage of the MOS technology powerdevice, and to the channel length. The accumulation region resistanceRacc depends on the distance “d” between two adjacent body regions, anddecreases as such distance decreases. The Rjfet resistance depends on aresistivity of the common drain layer and on the distance “d” betweenthe body regions, and increases as such a distance decreases. The Repiresistance depends on the resistivity and a thickness of the commondrain layer, two parameters which also determine a maximum voltage(Bvmax) that can be sustained by the MOS technology power device. Bvmaxincreases as the resistivity increases, as long as the epi layer isthick enough. The resistivity and the thickness are optimized for thelowest value of Repi. Further, the output resistance Ron is inverselyproportional to an overall channel length of the MOS technology powerdevice. In other words Ron is inversely proportional to a sum of thechannel of the individual elementary functional units that make up theMOS technology power device. The longer the channel length per unit areaof the MOS technology power device, the lower the output resistant Ronper unit area.

[0018] Thus, in order to reduce the Ron it is desirable to scale downthe dimensions of the elementary functional units and in particular thedistance “d” between the body regions as long as Rjfet is notsignificantly increased, or in other words to increase a density ofelementary functional units per unit area. A reduction of the distance“d” between the body regions has a further advantage of lowering theinput and feedback capacitances of the MOS technology power device, thusimproving its dynamic performance. Also, in high-voltage MOS technologypower devices, reducing the distance “d” between the body regionsincreases the device's ruggedness under switching conditions. A recenttechnological trend has therefore been toward increasing the density ofelementary functional units per unit area, and MOS technology powerdevices with a density of up to six million elementary cells per squareinch can be fabricated.

[0019] The structure of the related art however poses some limitationsto the further reduction of the dimensions thereof. These limitationsare essentially determined by a resolution and alignment characteristicsof the photolithographic apparatus used in the process to manufacturethe MOS technology power device. Referring again to FIG. 1, it is knownthat the dimension “c” must be sufficiently large enough to guaranteethat the metal layer 10 contacts the body region, and can only be scaleddown to the resolution limit of the photolithographic apparatus used toprovide the region “c”. In addition, the dimension “b” must besufficiently large enough to guarantee that the metal layer contacts thesource region 6, and must also allow for any alignment errors betweenthe mask defining the contact window 11 in the dielectric layer 9 andthe mask for the formation of the source regions. Further, the dimension“t” must be sufficiently large enough to guarantee that the polysiliconlayer 8 is electrically insulated from the metal layer and must alsotake into account any alignment errors between the masks for thedefinition of the windows 12 in the polysilicon layer and the mask forforming the contact windows in the dielectric layer.

[0020] In addition, the structure of the elementary functional unitsaccording to the related art does not allow reduction of the distance“d” between the elementary functional units below certain values thatdepend on a voltage rating of the MOS technology power device. Forexample, the distance “d” is approximately 5 μm for low-voltage devicesand in a range from 10 μm to 30 μm for medium- to high-voltage devices.A reduction of the distance “d” below the specified values would in factcause a rapid increase in the Rjfet component of the Ron of the MOStechnology power device, thereby increasing the value of Ron.

[0021] In view of the state of the art described, it is an object of thepresent invention to provide a new MOS technology power device structurewhich provides an improvement to the MOS technology power devices of therelated art.

SUMMARY OF THE INVENTION

[0022] It is an object of the present invention o provide a power devicehaving a higher scale of integration than the MOS technology powerdevices of the related art. In addition, it is an object of the presentinvention to provide a power device and a method for manufacturing ofthe power device that is not limited by the processing and alignmenttolerances of the MOS technology power device of the related art. Inparticular, it is an object to provide a power device having a dimensionLp that is a function of two features.

[0023] According to the present invention, such objects are attained bya MOS technology power device having a semiconductor material layer of afirst conductivity type and a plurality of elementary functional units.A first insulating material layer is placed above the semiconductormaterial layer and a conductive material layer is placed above the firstinsulating material layer. Each elementary functional unit includes abody region of a second conductivity type formed in the semiconductormaterial layer, wherein the body region is an elongated body region.Each elementary functional unit further includes a first elongatedwindow in the first insulating material layer and the conductivematerial layer, extending above the elongated body region. Eachelongated body region includes a source region doped with dopants of thefirst conductivity type, and intercalated with a body portion of thebody region wherein no dopant of the first conductivity type areprovided. In addition, each elementary unit includes a second insulatingmaterial layer disposed above the conductive material layer and thatinsulate edges of the first elongated window in the conductive materiallayer and the first insulating material layer from a metal layerdisposed above the second insulating material layer. The secondinsulating material layer having a second elongated window above theelongated body region The metal layer contacts each body region andsource region through the second elongated window of each elementaryfunctional unit.

[0024] In one embodiment of the MOS-technology power device, the sourceregion includes a plurality of source portions of the first conductivitytype that extend in a longitudinal direction of the elongated bodyregion and that are intercalated in the longitudinal direction with bodyportions of the elongated body region. In an alternative of thisembodiment, a length of the source portions is greater than a length ofthe body portions, and the source portions and the body portions of theelongated body region are substantially aligned in a directiontransverse to the longitudinal direction respectively with the sourceportions and the body portions in body regions of adjacent elementaryfunctional units. In another alternative of this embodiment, a length ofthe source portions is greater than a length of the body portions, andthe source portions and the body portions of the body stripe aresubstantially shifted in the longitudinal direction with respect to thesource portions and the body portions in the body regions of theadjacent elementary functional units.

[0025] In another embodiment of the MOS-technology power device, eachsource region includes a plurality of source portions extending in thelongitudinal direction of the elongated body region and intercalatedwith the body portions of the body region. A length of the sourceportions is substantially equal to a length of the body portions, andthe source portions and the body portions of the elongated body regionare substantially aligned in the transverse direction respectively withthe body portions and the source portions of the body regions of theadjacent elementary functional units.

[0026] In another embodiment of the MOS-technology power device, theelongated body region includes a first longitudinal half-stripe and asecond longitudinal half-stripe that are merged together along alongitudinal edge. Each half-stripe includes a plurality of sourceportions intercalated in the longitudinal direction with body portionsof the half-stripe. The source portions and the body portions of thefirst longitudinal half-stripe are aligned in the transverse direction,respectively, with the body portions and the source portions in thesecond longitudinal half-stripe.

[0027] In another embodiment of the MOS-technology power device, theelongated body region includes a first longitudinal half-stripe and asecond longitudinal half-stripe merged together along a longitudinaledge. The first longitudinal half-stripe includes an elongated sourceportions extending for substantially an entire length of the firstlongitudinal half-stripe. The second longitudinal half-stripe includesno dopants of the first conductivity type so that the elongated sourceregion is adjacent the body region for the entire length of theelongated body region.

[0028] For each of the embodiments of the present invention, theelongated body region of each elementary functional unit and the layoutof the source region inside the elongated body region allow the sourcemetal layer to contact the source region and the body region along thelength of the elongated body regions, and result in a reduced dimensionLp of the elongated opening in the first insulating material layer andthe conductive material layer in the direction transverse to the lengthof the elongated body region. Thus each of the embodiments of thepresent invention have a reduced dimension Lp of each elementaryfunctional unit, and an increased density of elementary functional unitsper unit area.

[0029] Also according to the present invention, there is provided aprocess for manufacturing a MOS technology power device, includingforming a first insulating material layer over a semiconductor materiallayer of a first conductivity type, forming a first conductive materiallayer over the first insulating material layer, and selectively removingthe first conductive material layer to open at least one first elongatedwindow therein. An elongated body region of a second conductivity typeis then formed in the semiconductor material layer under the firstelongated window, and a source region of the first conductivity type isformed in the elongated body region, in such a way as to be intercalatedin the longitudinal dimension with a body portion of the elongated bodyregion wherein no dopants of the first conductivity type are provided. Asecond insulating material layer is disposed above the first conductivematerial layer and along edges of the first elongated window, a secondelongated window is formed in the second insulating material and asecond conductive material layer is provided over the second insulatingmaterial layer, and contacts the source region and the elongated bodyregion through the second elongated window.

[0030] Preferably, the step of forming the elongated body regionincludes selectively introducing a dopant of the second conductivitytype into the semiconductor material layer using the first conductivematerial layer as a mask, without the need of a dedicated mask for theformation of a heavily doped deep body region at the center of theelongated body region of the elementary functional units. In addition,the step of forming the source region preferably involves deposition ofphotoresist layer over the surface of the chip, selective exposition ofthe photoresist layer to a light source through a photolithographicmask, and selective removal of the photoresist layer from the surface ofthe chip. The photoresist layer, and the first conductive material layerare used as an implantation mask for introducing dopants of the firstconductivity type to form the source regions in the body region. Thesteps for forming the source region eliminate a need to provide atolerance for any misalignment between the photolithographic mask usedfor etching the photoresist layer and a photolithographic mask used fordefining the elongated window. With this method, the transversedimension Lp of the elongated opening in the first insulating materiallayer and the conductive material layer, is reduced.

[0031] According to the present invention, the objects of the presentinvention can also be achieved with a MOS-gated apparatus, such as forexample a MOSFET, an IGBT, a MOS-gated thyristor (MCT) or otherMOS-gated power devices. A MOS-gated power device includes asemiconductor material of a first conductivity type that has a pluralityof body regions of a second conductivity type formed in a surface of thesemiconductor material. A source region of the first conductivity typeis formed in a surface of each of the body regions. A first insulatingmaterial layer is disposed above the surface of the semiconductormaterial layer and a conductive material layer is disposed above thefirst insulating material layer. The conductive material layer includesa plurality of first elongated windows that are disposed above each ofthe plurality of body regions. A second insulating layer is disposedabove the conductive material layer. A second elongated window is openedin the second insulating layer above the plurality of body regions andseals edges of the conductive material layer in the plurality of firstelongated windows from a metal layer disposed above the secondinsulating layer. The metal layer contacts each of the plurality of bodyregions and each of the plurality of source regions through theplurality of second elongated windows.

[0032] Further, according to the present invention a process formanufacturing the MOS-gated apparatus includes providing a semiconductorsubstrate including the semiconductor material layer of the firstconductivity type disposed over a highly doped semiconductor materiallayer, forming a first insulating material layer above the surface ofthe semiconductor material layer, and forming a conductive materiallayer above the first insulating material layer . The conductivematerial layer is selectively removed to provide the plurality of firstelongated windows in the conductive material layer that expose thesurface of the semiconductor material layer beneath each of theplurality of first elongated windows. The plurality of body regions ofthe second conductivity type are formed in the surface of thesemiconductor material layer through the plurality of first elongatedwindows in the conductive material layer. The source region of the firstconductivity type is also formed in each body region through theplurality of first elongated windows. An insulating layer is disposedabove the conductive material layer and along the edges of the firstelongated window. A second elongated window is opened in the insulatinglayer and a metal layer is provided above the insulating layer so as tocontact each body region and each source region through each secondelongated window in the insulating layer.

[0033] Other objects and features of the present invention will becomeapparent from the following detailed description when taken inconnection with the following drawings. It is to be understood that thedrawings are for the purpose of illustration only and are not intendedas a definition of the limits of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The foregoing and other objects and advantages will be more fullyappreciated from the following drawing in which:

[0035]FIG. 1 is a cross-sectional view of a MOS technology power deviceaccording to the prior art;

[0036]FIG. 2 is a top-plan view of a portion of MOS technology powerdevice according to a first embodiment of the present invention;

[0037]FIG. 3a is a cross-sectional view along line III-III in FIG. 2illustrating a first embodiment of a body region of the first embodimentof the present invention;

[0038]FIG. 3b is a cross-sectional view along line III-III in FIG. 2illustrating a second embodiment of a body region of the firstembodiment of the present invention;

[0039]FIG. 4a is a cross-sectional view along line IV-IV in FIG. 2illustrating a first embodiment of a body region of the first embodimentof the present invention;

[0040]FIG. 4b is a cross-sectional view along line IV-IV in FIG. 2illustrating a second embodiment of a body region of the firstembodiment of the present invention;

[0041]FIG. 5 is a top-plan view of the portion of MOS technology powerdevice shown in FIG. 2, illustrating alignment of some photolithographicmasks used for fabricating the device at an intermediate step of themanufacturing process.

[0042] FIGS. 6-13 are cross-sectional views illustrating some of thesteps of a manufacturing process of the MOS technology power device ofFIG. 2.

[0043]FIG. 14 is a top-plan view of a portion of MOS technology powerdevice according to a second embodiment of the present invention;

[0044]FIG. 15 is a cross-sectional view along line XV-XV in FIG. 14;

[0045]FIG. 16 is a cross-sectional view along line XVI-XVI in FIG. 14;

[0046]FIG. 17 is a cross-sectional view along line XVII-XVII in FIG. 14;

[0047]FIG. 18 is a top-plan view of the portion of MOS technology powerdevice shown in FIG. 14, illustrating alignment of somephotolithographic masks used for fabricating the device at anintermediate step of the manufacturing process;

[0048]FIG. 19 is a top-plan view of a portion of MOS technology powerdevice according to a third embodiment of the present invention;

[0049]FIG. 20 is a cross-sectional view along line XX-XX in FIG. 19;

[0050]FIG. 21 is a cross-sectional view along line XXI-XXI in FIG. 19;

[0051]FIG. 22 is a top-plan view of the portion of MOS technology powerdevice shown in FIG. 19, illustrating alignment of somephotolithographic masks used for fabricating the device at anintermediate step of the manufacturing process;

[0052]FIG. 23 is a top plan view of a portion of MOS technology powerdevice according to a fourth embodiment of the present invention;

[0053]FIG. 24 is a cross-sectional view along line XXIV-XXIV in FIG. 23;

[0054]FIG. 25 is a cross-sectional view along line XXV-XXV in FIG. 23;

[0055]FIG. 26 is a top-plan view of the portion of MOS technology powerdevice shown in FIG. 23, illustrating alignment of somephotolithographic masks used for fabricating the device at anintermediate step of the manufacturing process;

[0056]FIG. 27 is a top-plan view of a portion of MOS technology powerdevice according to a fifth embodiment of the present invention;

[0057]FIG. 28 is a cross-sectional view along line XXVIII-XXVIII in FIG.27; and

[0058]FIG. 29 is a top-plan view of the portion of the MOS technologypower device of FIG. 27 illustrating alignment of some photolithographicmasks used for fabricating the device at an intermediate step of themanufacturing process.

DETAILED DESCRIPTION

[0059] As discussed above, FIG. 1 is a cross-sectional view of a MOStechnology power device chip according to the related art. The powerdevice chip includes a heavily doped semiconductor substrate 1, and alightly doped epitaxial layer 2 of a first conductivity type formed overthe semiconductor substrate. The MOS technology power device includes aplurality of elementary functional units formed in the epitaxial layer2. Two of the elementary functional units are illustrated in FIG. 1.

[0060] Each elementary functional units includes a body region 3 of asecond conductivity type formed in the epitaxial layer 2. Each bodyregion 3 can have a polygonal layout, such as for example a square or ahexagonal shape, or can be formed as an elongated stripe that has alongitudinal direction in a direction into the Figure. In other words,FIG. 1 is a cross-sectional view in a direction transverse to a lengthof the elongated stripes. The body region includes a central heavilydoped portion 4, called a “deep body region”, and a lateral portion 5,having a lower dopant concentration, and which forms a channel region ofthe elementary functional unit. A doping level of the lateral portion 5of the body region determines a threshold voltage of the power device.The threshold voltage is the voltage at which the device begins toconduct. Inside each body region 3, is a source region 6 of the sameconductivity type as the epitaxial layer 2. A thin oxide layer 7 (a gateoxide layer) and a polysilicon layer 8 cover a surface of portions ofthe epitaxial layer 2 between the body regions 3 of the two elementaryfunctional units, and extend over the lateral portions 5 of the bodyregions 3 in each functional unit. A window 12 is provided in thepolysilicon and gate oxide layers 8, 7 over the body region 3, and inparticular over a surface of each source region and a surface of thedeep body region. The polysilicon layer 8 is covered by a dielectriclayer 9 in which a contact window 11 is opened over each body region 3,to expose a surface of an inner-portion of each of the source regionsand a surface of the deep body region. A metal layer 10 making up thesource electrode of the power device is placed over the dielectric layerand contacts the surface of the source regions 6 and the surface of thedeep body region 4 through the contact window.

[0061] A size of each elementary functional unit of the MOS power deviceis a function of a dimension Lp of the window 12 in the polysiliconlayer 8 and the gate oxide layer 7. As discussed above and illustratedin FIG. 1, the dimension Lp is a function of the features “a” and “t” asdefined in equation (1):

Lp=a+2t  (1)

[0062] where “a” is the width of the contact window 11 in the dielectriclayer 9 and “t” is the distance between an edge of each of thepolysilicon layer 8 and gate oxide layer 7 and an edge of the dielectriclayer 9. The width “a” of the contact window is defined in equation (2):

a=c+2b  (2)

[0063] where “b” is a distance between an edge of the contact window 11in the dielectric layer 9 and an inner edge of the source region 6 or inother words the length of the surface of source region available to becontacted by the source metal layer 10, and “c” is the length of thesurface of the deep body region wherein the source regions 6 are absentor in other words the distance between the inner edges of the sourceregions 6 corresponding to the length of the surface of the deep bodyregion 3 available to be contacted by the source metal layer 10. Thedimension Lp is therefore given by equation (3):

Lp=c+2b+2t  (2).

[0064] The dimension Lp of each elementary functional unit of therelated art is therefore determined by the three feature sizes “c”, “b”and “t”.

[0065] As discussed above, it is desirable to reduce the outputresistance of the power device in the “on” condition by decreasing thesize of each elementary functional unit of the MOS technology powerdevice. In order to reduce the size of each elementary functionallyunit, it is desirable to scale down the distance “d” between each of theelementary functionally units thereby resulting in an increase in thedensity of the elementary functional units per unit area of the MOStechnology power device. In addition, as discussed above, the reductionin the distance “d” between the elementary functional units of the MOStechnology power device has added advantages of lowering thegate-to-source capacitance (the input capacitance) and the gate-to-draincapacitance (the feedback capacitance) of the MOS technology powerdevice, thereby resulting in an improvement in the dynamic performanceof the MOS technology power device. Further, an added advantage ofreducing the distance between the elementary functional units for ahigh-voltage MOS technology power device is that the high-voltage MOStechnology power device is more rugged under switching conditions. Thedistance “d” cannot be reduced too much however, or Rjfet begins toincrease. Therefore, it is an object of the power device of the presentinvention to increase the density of the elementary functional units perunit area.

[0066] A problem with the MOS technology power device of the related artillustrated in FIG. 1, is that each of the three features “c”, “b”, and“t” has a minimum possible size which is determined by a resolutionlimit and by alignment characteristics of a photolithographic apparatusused in the process of manufacturing the MOS technology power device. Inparticular, the distance “c” between the inner edges of the sourceregions must be large enough to provide sufficient area for the metallayer 10 to contact the surface of the deep body region 4. In addition,the distance “b” between the edge of the contact window 11 and the inneredge of each of the source regions 6 must also be large enough toprovide an area sufficient for the metal layer 10 to contact the surfaceof each of the source regions 6, and must also be large enough toaccount for any alignment errors of the mask used to define the contactwindow 11 in the dielectric layer and the mask used to form the sourceregions 6 and the body region 3. Further, the distance “t” between theedges of the polysilicon layer 8 and the oxide layer 7 and the edge ofthe window 11 in the dielectric layer 9 should be large enough to insurethat the polysilicon layer is electrically insulated from the metallayer, and also to take into account any or errors between the mask fordefining the window 12 in the polysilicon and oxide layers and the maskfor defining the contact window 11 in the dielectric layer. Stillfurther, the distance “d” between each of the elementary functionalunits is limited by a voltage rating desired for the MOS power device.For example, low-voltage power MOS devices typically have the distance“d” of approximately 5 μm while medium-voltage and high-voltage devicestypically have the distance “d” in the range from 10 μm to 30 μm. As isknown in the related art, reducing the distance “d” below these valuesresults in an increase in the output resistance Ron of the MOS powerdevice. Accordingly, the structure of the MOS power device of therelated art has limits to which the size of each elementary functionalunit can be decreased. The power device of the present inventionimproves upon the MOS power device of the related art with a structurethat is reduced in size and provides an increased density per unit area.

[0067] In the following description, the reference numerals used in FIG.1 will be used to indicate similar parts.

[0068]FIG. 2 is a top-plan view of a portion of a MOS-gated power deviceaccording to a first embodiment of the present invention. It is to beappreciated that the term MOS-gated includes MOS power devices includingMOSFETS, IGBTs, MOS-gated thyristors (MCT) and other MOS-gated powerdevices. As illustrated in FIG. 2 and in conjunction withcross-sectional views of FIGS. 3 and 4, the MOS-gated power devicecomprises a lightly doped semiconductor layer 2 of a first conductivitytype, such as for example an epitaxial layer, superimposed over aheavily doped semiconductor substrate 1. FIGS. 3 and 4 are across-sectional view taken along lines III-III and IV-IV respectively ofFIG. 2. In particular, FIGS. 3a and 4 a illustrate a first embodiment ofthe body region of the first embodiment of the MOS-gated power device ofthe present invention and FIGS. 3b, 4 b illustrate a second embodimentof the body region. The epitaxial layer 2 forms a common drain layer ofthe MOS-gated power device, and can be either of the N conductivity typefor an N-channel device, or of the P conductivity type for a P-channeldevice. For a power MOSFET the substrate 1 is of the same conductivitytype as the epitaxial layer 2, whereas for an Insulated Gate BipolarTransistor (IGBT) the substrate 1 and the epitaxial layer 2 are ofopposite conductivity types. The MOS-gated power device includes aplurality of elementary functional units formed in the epitaxial layer2. Each elementary functional unit includes a body region 3 of theopposite conductivity type of the epitaxial layer 2. As illustrated inFIG. 2, the body regions 3 can be substantially parallel elongatedstripes spaced apart by the distance “d” from each other. However, it isto be appreciated that the body regions can be any elongated shape suchas for example, an elongated polygon. Inside each body stripe 3, aplurality of heavily doped regions 60 of the opposite conductivity typefrom the body stripe 3 are provided. The heavily doped regions 60 extendin the longitudinal direction of the body stripe 3, and are intercalatedwith body portions 40 of the body stripe 3. The heavily doped regions 60form source regions of the MOS-gated power device.

[0069] The surface of the drain layer 2 is covered by a gate oxide layer7, such as for example silicon dioxide, and a conductive layer 8, suchas for example polysilicon, that forms the gate electrode of theMOS-gated power device. The gate oxide layer 7 and the polysilicon layer8 cover the surface of the epitaxial layer between the body stripes 3and extend over the stripes 3 to the edges of the regions 60. Adielectric layer 9 covers the polysilicon layer 8. Elongated openings 11(contact windows) are provided in the dielectric layer 9 over thecentral portion of the stripes 3 to allow a metal layer (not shown)forming the source electrode of the MOS-gated power device to contactboth the source regions 60 and the body portions 40 of the body stripes3 through the elongated openings.

[0070] As illustrated in FIG. 3, the transverse dimension Lp of thewindow in the polysilicon and gate oxide layers 8 and 7 is given by:

Lp=a+2t

[0071] where a is the transverse dimension of the contact window 11 andt is the distance between the edge of the polysilicon layer and the edgeof the dielectric layer 9. However, the structure of the presentinvention, is different from the related art structure because thesource regions 60 are intercalated in the longitudinal direction of thebody stripes 3 with the portions 40 of the body stripes 3 wherein thesource regions are absent. Because the elementary functional unitsinclude the elongated body stripes with source regions 60 intercalatedin the longitudinal direction with body portions 40 of the body stripe,the contact of the source metal layer to both the source regions and tothe body stripes is provided in the longitudinal direction. Thiseliminates the problems associated with the related art structure shownin FIG. 1. In particular, it is not necessary with the structure of thepresent invention to provide the distance “b” between the edge of thecontact window 11 in the dielectric layer and the inner edge of thesource regions. Therefore, the dimension Lp of the structure of thepresent invention is not a function of the feature size “b”. Thus, withthe structure of the present invention, even if the transverse dimension“a” of the contact window 11 is scaled down to the optical resolutionlimit of the photolithographic apparatus used for the fabrication of theMOS-gated power device, the contact of the source metal layer (notshown) to both the source regions 60 and the body region 3 of theelementary functional units is guaranteed.

[0072] With the structure and method of manufacturing of the presentinvention, the dimension Lp of the elongated openings 12 in the gateoxide layer 7 and the polysilicon layer 8 can be scaled down to theoptical resolution limit “f” of the photolithographic apparatus used todefine the openings 12 plus twice the distance “t” between the edge ofthe window 12 in the polysilicon layer and the edge of the contactwindow 11 in the dielectric layer. In other words, in the structureaccording to the present invention, the minimum value of Lp is f+2t. Bycomparison, as discussed above, the related art structure minimum valueof Lp is c+2b+2t, and the dimension Lp of the elementary functional unitis determined by the three feature sizes.

[0073] Referring to FIG. 2, it can be appreciated that the channelperimeter of the MOS-gated power device is proportional to the ratio:

Lu/(Lu+s)

[0074] where Lu is a length of a source region 60 in the longitudinaldirection of the body stripe 3, and “s” is the distance between twoconsecutive source regions 60, or in other words “s” is a length of thebody portions 40 of the body stripes wherein the source regions areabsent. The body portions 40 of the body stripes 3 are functionallyinactive areas of the MOS-gated power device in that they do notcontribute to the overall current conduction of the power device. Aspreviously mentioned the “on” resistance Ron of the output resistance ofthe MOS-gated power device is inversely proportional to the overallchannel perimeter of the power device, thus a smallest Ron is achievedby making “s” as small as possible and Lu as large as possible. Aminimum value for “s” is given by an optical resolution limit “f” of thephotolithographic apparatus, while a maximum value for Lu depends on theparticular technology and voltage rating desired of the MOS-gated powerdevice. In addition, the greater the distance Lu between two consecutivecontacts to the body stripe 3 via the body regions 40, the higher thebase resistance of a parasitic bipolar junction transistor that isintrinsically associated with the structure formed by the source regions60, the body stripe 3 and the epitaxial layer 2, and the lower themaximum current that the MOS-gated power device can withstand duringswitching. As a consequence, the greater the distance Lu, the greaterthe likelihood that the MOS-gated power device cannot sustain a maximumspecified voltage. Accordingly, there is a tradeoff between the Ron ofthe device and the maximum current capacity of the device, and thevalues of Lu and “s” should be selected accordingly.

[0075] In the embodiment of the present invention illustrated in FIGS.2-4, the source regions 60 in adjacent body stripes 3 are aligned in atransversal direction of the body stripes. In other words. the sourceregions 60 and the body regions 40 in one body stripe are respectivelyaligned in the direction transverse to the length of the body regions 3with the source regions and the body regions in the elongated bodyregions of the adjacent elementary functional units. In the epitaxiallayer 2 between the adjacent body stripes 3 there are two current fluxesI as illustrated in FIG. 3, which run from facing source regions 60 inthe adjacent body stripes 3. The distance “d” between adjacent bodystripes 3 cannot therefore be reduced beyond a certain limit or Rjfetincreases dramatically.

[0076]FIG. 5 is a top-plan view illustrating the layout and thereciprocal alignment of the photolithographic masks used to fabricatethe MOS-gated power device structure of the embodiment shown in FIGS.2-4. In the figure, 15 indicates the mask for the selective etching ofthe polysilicon and gate oxide layers, 16 indicates the mask for theselective introduction of the dopants forming the source regions 60, and17 (in dash-and-dot line) indicates the mask for the opening of thecontact windows 11 in the dielectric layer 9.

[0077] A process for manufacturing the MOS-gated power device accordingto the present invention is illustrated in FIGS. 6-13. FIG. 6illustrates the initial step of epitaxially growing the lightly dopedsemiconductor layer 2 over the heavily doped semiconductor substrate 1.If the power device to be formed is a power MOSFET, the substrate 1 andthe epitaxial layer 2 are of the same conductivity type, whereas if anIGBT is to be fabricated, the substrate and the expitaxial layer are ofopposite conductivity types. Other MOS-gated power devices may requiredifferent combinations of substrates and epitaxial layers and areintended to be within the scope of this disclosure. A resistivity and athickness of the epitaxial layer 2 grown over the heavily dopedsemiconductor substrate are chosen to yield a voltage class of the powerdevice. For example, low-voltage and high-voltage power devices usuallyhave a respective resistivity in a range from 0.5 Ohm cm to 100 Ohm cm,and a thickness in a range from 3 μm to 100 μm. The silicon dioxidelayer 7 (the gate oxide layer) is then formed over a surface of theepitaxial layer, by a thermal oxidation process. For example, thesilicon dioxide can be formed by a conventional process of forming athick oxide layer over the surface of the epitaxial layer, masking andetching of the thick oxide layer to define active areas of the MOS-gatedapparatus, and forming the thin gate oxide layer over the surface of theepitaxial layer in the active areas, can be used to form the gate oxidelayer 7. The polysilicon layer 8 is then formed over the gate oxidelayer 7. In one embodiment, the polysilicon layer is then doped toreduce its resistivity. Alternatively, or even in addition to this step,a layer of silicide (for example cobalt silicide) can also be formedover the polysilicon layer 8 by depositing over the surface of thepolysilicon layer 8 a layer of cobalt, and by performing a heatingprocess such as submitting the device to a temperature of about 500° C.so that the cobalt and silicon react to form the silicide layer (notillustrated). An advantage of the silicide layer is that the silicidelayer greatly reduces the gate resistance of the MOS-gated power device.

[0078] According to one embodiment of the process of manufacturing theMOS-gated power device having the body region as illustrated in FIGS. 3aand 4 a, a first step for forming the central heavily doped portion ofthe body regions is to implant a high dose of, for example, P-typedopants through a first mask into the epitaxial layer to form thecentral heavily doped portions of the body regions (step notillustrated). Referring now to FIG. 7, the polysilicon layer 8 is thenselectively etched by the photolithographic mask 15 (See FIG. 5) to openthe elongated windows in the polysilicon layer 8 where the elementaryfunctional units of the MOS power device will be formed. Thephotolithographic mask 15 is formed by depositing a photoresist layerover the polysilicon layer, selectively exposing the photoresist layerby the photolithographic mask 15 to a light source, and selectivelyremoving the photoresistive layer from regions of the polysilicon layerwhich are to be etched away (steps not illustrated). It is to beappreciated that although not illustrated in FIG. 7, the gate oxidelayer 7 may also be selectively etched at the same time as thepolysilicon layer 8 to form the elongated windows, or in the alternativeit can be etched at a later step after opening the source contactwindows 11 in the dielectric layer, to be discussed below. It isapparent that the regions of the polysilicon layer 8 that are stillcovered by the photoresist layer are not subject to the etchingdescribed above. The lateral lightly doped portions of the body regionsillustrated in FIGS. 3a, 4 a are then formed by implanting through theelongated windows in the polysilicon layer a low dose of, for exampleP-type dopants, to form the lateral lightly doped portions of the bodyregions (step not illustrated).

[0079] In another embodiment of the process of manufacturing theMOS-gated power device of the present invention, having the body regionsas illustrated in FIGS. 3b and 4 b, the body regions having the“bowl-like” shape can be formed by one of two processes. An advantage ofthe body regions having the bowl-like shape is that the first mask usedto implant the central heavily doped deep body region as discussed abovewith respect to the process for forming the body region illustrated inFIGS. 3a, 4 a is not needed. In contrast, the body regions having the“bowl-like” shape can be implanted into the epitaxial layer through theelongated windows in the polysilicon layer 8 using the polysilicon layer8 as the mask.

[0080] A first process of forming the body regions 3 having the“bowl-like” shape will now be described. Referring to FIG. 8, a highdose of a dopant of the second conductivity type is implanted at a highenergy into the epitaxial layer 2 through the elongated openings,wherein the polysilicon layer 8 acts as an implant mask for the dopantions. For example, boron ions can be implanted in a dose of 10¹³-10¹⁵cm² at an energy of 100-300 keV. With the high implantation energy, theregions 14 of the second conductivity type are formed in the epitaxiallayer 2 wherein the distribution of the implanted ions has a peakconcentration located at a prescribed distance from the surface of theepitaxial layer 2. An actual value of prescribed distance depends on theimplantation energy, and preferably the implantation energy is such asto locate the peak concentration of dopants the prescribed distance intothe epitaxial layer that is deeper than the source regions which will beformed in a later step to be described below. In addition, because thepolysilicon layer 8 is used as the mask, the distribution of theimplanted ions is laterally aligned with the edges of the window in thepolysilicon layer.

[0081] Referring now to FIG. 9, the implanted ions are then made todiffuse laterally and into the epitaxial layer by a thermal process toform the body stripes 3. The thermal process has a temperature and atime duration chosen in such a way that the body stripes 3 have acentral heavily doped deep body stripe 17, which is formed by verticaldiffusions of the dopants into the epitaxial layer, having elongatededges substantially aligned with the edges of the elongated openings inthe polysilicon layer 8, and two lateral lightly doped channel stripes18 laterally extending under the gate oxide layer 7, which are formed bylateral diffusion of the dopants into the epitaxial layer. A suitablethermal process can be for example at a temperature of 1050-1100° C. for0.5 to 2 hours. Thus, the process according to this embodiment of theinvention uses only one dopant implant step, does not need multiplesteps, and does not need the first mask as is needed in the process ofthe related art.

[0082] An alternative method of forming the “bowl-like” shaped bodystripes 3 involves two distinct implants of dopants of the secondconductivity type into the epitaxial layer 2, in different doses and atdifferent energies, again using the polysilicon layer 8 as theimplantation mask for both of the implants. For example, a first implantcan involve a dose of dopants in a range of 10¹³ to 10¹⁴ atoms/cm² withan energy of approximately 80 keV to provide a dopant concentration atthe surface of a body stripe, for example in the channel portions. Inaddition, the first dopant can be used to set the desired thresholdvoltage of the MOS-gated power device. It is to be appreciated thatalthough it is not needed, there may also be a thermal diffusion stepbetween the first implant and a second implant. The second implant canthen be for example, a dose of a dopant in the range of 10¹⁴ to 10¹⁵atoms/cm² with an energy in a range between 100 keV and 300 keV, suchthat a peak concentration of the dopants can be located at theprescribed distance, namely at a distance deeper than the source regionswhich will be formed in a later step. A thermal diffusion at atemperature for example in the range from 1050-1100° C. for 0.5 to 2hours is then performed to provide the lateral diffusion of the dopantintroduced with the first implant to form the channel portions of thebody stripes extending under the gate oxide layer. Any verticaldiffusion of the dopant introduced with the second implant during thisthermal step does not alter the threshold voltage of the MOS-gated powerdevice, because any dopant ions that reach the surface of the epitaxiallayer have a concentration lower than the concentration of the dopantintroduced with the first implant, since the peak dopant concentrationof the dopant introduced with the first implant is located substantiallyat the surface of the epitaxial layer 2. The vertical and lateraldiffusion of the dopants introduced with the second implant form theheavily doped deep body regions of the body stripes, and reduce theresistivity of the body stripes under the source regions. Each of theabove processes for forming the “bowl-like” body region shape have theadvantages of providing the central heavily doped body strip that isself-aligned with the edges of the elongated windows, and uses one lessmasking step than the process of the related art structure.

[0083] Referring now to FIGS. 10-11, which respectively showcross-sectional views of the body stripes not covered by a photoresistlayer 150 and covered by the photoresist layer after the body stripes 3have been formed by any of the above processes, dopants of the firstconductivity type are selectively introduced into the body stripes in aheavy dose using the photolithographic mask 16 (See FIG. 5) to form thesource regions of the power device. In particular, this step involvesdeposition of the photoresist layer 150 over the surface of the chip asillustrated in FIG. 11, selective exposition of the photoresist layer toa light source through the photolithographic mask 16 so that the patternof the photolithographic mask is transferred to the photoresistivelayer. The photoresistive layer is then selectively removed from thesurface of the chip, to obtain the patterns of the photoresistive layeras shown in FIG. 5. The photoresistive layer acts as implantation maskfor dopants of the first conductivity type as shown in FIG. 11. Withthese steps, the source regions 60 are formed in the body regions 3 asillustrated in FIG. 10 and are intercalated in the longitudinaldirection of the body stripes with the portions 40 of the body stripesas illustrated in FIG. 11.

[0084] It is to be appreciated that the source regions within each bodyregion, can also be formed by using a silicon etching step to etchportions of a source region diffused in the body region. For example,the source region may be implanted as an elongated stripe within theelongated body region. The body portions of the body region can then beformed by etching through the source stripe to the underlying bodyregion to provide the plurality of body portions and source regionswithin the body region.

[0085] One advantage of the process of manufacturing the MOS-gated powerdevice according to the present invention is that should a misalignmentexists between the photolithographic mask 16 used for defining patternof the photoresistive layer 150 and the photolithographic mask 15 usedfor defining the elongated openings in the polysilicon layer 8, themisalignment does not have any effect on the final structure because thesource region 60 will be intercalated in the longitudinal direction ofthe body regions with the body portions 40 of the body regions. In otherwords, the transverse dimension of the structure of the presentinvention is not being relied upon to establish connection of the metallayer 10 to each of the source region and the body region. Instead thelongitudinal dimension is used to provide these contacts.

[0086] Another advantage of the process and structure of the presentinvention is that the processing step for forming the “bowl-like” bodyregion of the present invention does not need the mask for the formationof the deep body region portion, as required in the process of therelated art. In particular, as discussed above, the related art requiresa first mask internal to the openings 12 in the polysilicon layer, thatis used to introduce the high dose of dopants into the semiconductorlayer to form the central portion of the deep body regions whileavoiding lateral diffusion of the dopants in the channel regions and asecond mask (the elongated windows) in the polysilicon layer forimplanting the low dose of dopants to form the lateral lightly dopedregions. In contrast, the polysilicon layer is used as the mask forintroducing the dopants to create the body regions according to thepresent invention, and no other mask is needed.

[0087] Referring now to FIGS. 12-13, which illustrate thecross-sectional views of FIGS. 3b, and 4 b respectively, there isillustrated the body regions 3 containing the source portions 60 and thebody portions, respectively. The photoresist layer 150 is removed. Inaddition, it is to be appreciated that if the underlying gate oxidelayer 7 had not been removed simultaneously with the polysilicon gatelayer 8 as discussed above, then the underlying gate oxide layer is thenremoved simultaneously with the photoresistive layer. The dielectriclayer 9, such as for example an oxide layer formed by a chemical vapordeposition and doped with P-type dopants (known as “PVAPOX”) is thendeposited over the substrate and selectively etched using thephotolithographic mask 17 (See FIG. 5) to form the contact windows 11 inthe dielectric layer 9. The metal layer (not shown) is then depositedover the dielectric layer 9 and it is selectively removed to define thesource electrode of the MOS power device.

[0088]FIG. 14 is a top-plan view of a portion of a MOS-gated powerdevice according to a second embodiment of the present invention. FIGS.15, 16 and 17 illustrate cross-sectional views of the epitaxial layer 2taken along lines XV-XV, XVI-XVI, and XVII-XVII, respectively. Thisembodiment is substantially similar to that of FIG. 2, except that thesource regions 60 in a given body stripe 3 are shifted in thelongitudinal direction with respect to the source regions 60 in theadjacent body stripes 3. With the structure of this embodiment, asillustrated in the cross-sectional views of FIGS. 15, 16 and 17, thereare portions of the epitaxial layer 2 between adjacent body stripes 3wherein there is only one current flux I running either from the sourceregion 60 of one body stripe 3 or from the source region 60 of anadjacent body stripe 3. With this arrangement, it is possible toslightly reduce the distance “d” between the body stripes 3 withoutincreasing the resistance component Rjfet between depletion regions ofthe elementary functional units, which contributes to the overallresistance of the Ron. The increased integration density provides anincrease of the overall channel perimeter per unit area. However, sinceas discussed above in order to maximize the channel perimeter of thedevice the dimension s should be small compared with the dimension Lu,any reduction in the distance “d” should also should be small, becausethe majority of portion of the epitaxial layer 2 between the bodystripes 3 will have a current flow of two current fluxes I asillustrated in the cross-sectional view of FIG. 17.

[0089] The MOS-gated power device according to this second embodimentcan be fabricated using the same manufacturing process described above.In addition, it is to be appreciated that although FIGS. 14-17illustrate the body stripes 3 as having a central deep heavily dopedbody region and lightly doped lateral regions to form the shape asillustrated in the cross-sectional views of FIGS. 3a and 4 a, the bodyregions may also be formulated with the “bowllike” shape as illustratedin FIGS. 3b and 4 b.

[0090]FIG. 18, similar to FIG. 5, is a top-plan view illustrating thelayout and the reciprocal alignment of the photolithographic masks usedto form the MOS-gated power device structure according to this secondembodiment. In FIG. 18, reference numeral 15 indicates the mask for theselective etching of the polysilicon layer 8, 16 indicates the mask forthe selective introduction of the dopants forming the source regions 60,and 17 (in dash-and-dot line) indicates the mask for the opening of thecontact windows 11 in the dielectric layer 9. To take into account anyalignment tolerances of the photolithographic apparatus, a distance ebetween the windows 12 in the polysilicon layer should be larger thantwice an alignment tolerance Lt of the photolithographic apparatus, toprevent a misalignment in the transverse direction between the mask 15and the mask 16. However, this does not adversely affect the reductionin size achieved with the present invention because the alignmenttolerance of a photolithographic apparatus is normally smaller(approximately ¼) than the optical resolution limit “f” of thephotolithographic apparatus, and the dimension “e” is normally largerthan the optical resolution limit “f” of the photolithographicapparatus. For example, using a stepper photolithographic apparatus withan optical resolution “f” approximately equal to 1 μm, the alignmenttolerance is approximately 0.3 μm.

[0091] With each of the first two embodiments illustrated in FIGS. 2-4and 14-17 it is possible to obtain, with the same manufacturingprocesses already in use, low-voltage MOS-gated power devices with1200-4000 cm of channel perimeter per cm of active area depending on thephotolithographic apparatus in use and depending on process parameterssuch as the channel length. This channel perimeter per active areadensity is equivalent to a cellular MOS-gated power device with a celldensity ranging from 1.2 to 10 millions cells per square inch.

[0092]FIG. 19 is a top-plan view of a portion of a MOS-gated powerdevice according to a third embodiment of the invention. In thisembodiment the length “s” of the body portions 40 of the body stripes 3wherein the source regions 60 are absent is the same length as thelength Lu of the source regions 60. The channel perimeter for a singleelementary functional unit is therefore approximately one half of thatachievable with the structures of the previous two embodiments. However,this embodiment has an advantage for example with respect to theembodiment of FIGS. 2-4, in that the distance “d” between adjacent bodystripes 3 can be reduced to one half. This reduction in the distance “d”is possible because the source regions 60 of a given body stripe 3always face the body portions 40 of the adjacent body stripes 3. Asillustrated in the cross-sectional views of FIGS. 20-21, which are takenalong lines XX-XX and XXI-XXI of FIG. 19 respectively, the portions ofthe epitaxial layer 2 between the body stripes 3 are always intersectedby a current flux I coming from only one source region. An advantage ofthis embodiment of the present invention is that the reduction of thedistance “d” between the body stripes 3 leads to a lowering of thefeedback capacitance of the MOS-gated power device, because the areabetween the polysilicon layer 8 and the common drain layer 2 is reducedin half. This is of great benefit for the dynamic performance of thedevice. It is also to be appreciated that the reduction of the distance“d” between adjacent elementary functional units provides an increase ofthe integration density, and thus an overall channel perimeter per unitarea of this embodiment is higher than that achievable with structuresof the previous two embodiments.

[0093] The MOS-gated power device according to this third embodiment ofthe invention can be fabricated by the manufacturing process previouslydescribed. In addition, it is to be appreciated that although FIGS.19-23 illustrate the third embodiment as having the shape as shown inFIGS. 3a and 4 a, the body regions can also have the “bowl-like” bodyshape as illustrated in FIGS. 3b and 4 b.

[0094]FIG. 22 is analogous to FIGS. 5 and 18, and is a top-plan viewshowing the layout and the reciprocal alignment of the photolithographicmasks used to fabricate the structure of FIG. 19. Again, the mask forthe selective etching of the polysilicon layer is indicated withreference numeral 15, the mask for the selective introduction of thedopants for the source regions 60 is indicated with 16, and the mask forthe opening of the contact windows 11 is indicated with 17 (indash-and-dot lines). As in the case of the second embodiment and asillustrated in FIG. 18, the distance “e” between adjacent elongatedwindows 12 in the polysilicon layer 8 should be greater than twice thealignment tolerance Lt of the photolithographic apparatus in use, totake into account the possible alignment errors between the mask 15 andthe mask 16. However, as discussed above, this does not adversely affectthe reduction in size achieved with this embodiment because as alreadymentioned the alignment tolerance Lt is approximately ¼ of the opticalresolution limit. In addition, even though this embodiment allows asignificant reduction of the distance “d” between adjacent body stripes,the dimension “e” is larger than the optical resolution limit of thephotolithographic apparatus.

[0095]FIG. 23 is a top-plan view of a portion of a MOS-gated powerdevice according to a fourth embodiment of the invention. In thisembodiment, each body stripe 3 is divided into two longitudinalhalf-stripes 3′ and 3″, and in each half-stripe source regions 61 of theopposite conductivity type of the body stripe 3 are intercalated in thelongitudinal direction with body portions 41 of the half-stripe whereinthe source regions are absent. In addition, the source regions 61 in onehalf-stripe are contiguous to the body portions 41 of the otherhalf-stripe, and face the body portions 41 of adjacent body stripes 3.

[0096] As is the case with the structure illustrated in FIGS. 19-21, thearrangement of this embodiment allows a reduction in the distance “d”between adjacent body stripes, because the portions of the epitaxiallayer 2 between the adjacent body stripes 3 are always interested by acurrent flux I from only one source portion. FIGS. 24 and 25 arecross-sectional view taken along lines XXIV-XXIV and XXV-XXV of FIG. 23,respectively, and illustrate the single current flux I in the epitaxiallayer.

[0097] An advantage of this embodiment with respect to the previousthree embodiments is that the source metal layer 10 (not shown) contactsthe body stripes 3 and the source regions 61 along their whole length,instead of at regularly spaced intervals having the length equal to Lu.This results in an increased ruggedness of the MOS-gated power device.For example, a base-emitter resistance of a parasitic bipolar junctiontransistor associated with the structure formed by the source regions,the body stripes and the epitaxial layer is minimized.

[0098] The MOS-gated power device according to this third embodiment ofthe invention can be fabricated by the same manufacturing processpreviously described. In addition, it is to be appreciated that althoughFIGS. 24-25 illustrate the fourth embodiment as having the shape asshown in FIGS. 3a and 4 a, the body regions can also have the“bowl-like” body region shape as illustrated in Figs, 3 b and 4 b.

[0099]FIG. 26 is analogous to FIGS. 5, 18 and 22, and is a top-plan viewshowing the layout and the reciprocal alignment of the photolithographicmasks used to fabricate the structure of FIG. 23. Again, referencenumeral 15 indicates the mask for the selective etching of thepolysilicon layer 8, 16 indicates the mask for the formation of thesource regions 61, and 17 (in dash-and-dot lines) indicates the mask forthe opening of the contact windows 11 in the dielectric layer 9. It canbe appreciated that the layout of the three masks is substantially thesame as that of FIG. 22, the only difference for this embodiment notonly should the distance “e” between adjacent elongated windows 12 inthe polysilicon layer be greater than twice the alignment tolerance Ltof the photolithographic apparatus in use, but also the dimension “a” ofthe contact window should be greater than 2Lt, to prevent any alignmenterrors between mask 15 and mask 16 yielding an incorrect layout.However, since the minimum value for dimension “a” is the opticalresolution limit of the photolithographic apparatus, and since thealignment tolerance Lt is approximately ¼ the optical resolution limit,the possibility of alignment errors between masks 15 and 16 does notpose a limit to shrinking the transverse dimension of the elementaryfunctional units with this embodiment. An advantage of this embodimentof the present invention is that the contact of the source metal layer(not shown) to the source regions 61 and to the body portions 41 isguaranteed even if the dimension “a” of the elongated contact window 11is reduced to the optical resolution limit of the photolithographicapparatus.

[0100]FIG. 27 is a top-plan view of a MOS-gated power device accordingto a further embodiment of the present invention. As in the case of theembodiment illustrated in FIG. 23, each body stripe 3 is divided in twohalf-stripes 3′ and 3″. In a first half-stripe of the two half-stripes asource region 62 is provided that extends substantially for an entirelength of the body stripe 3, while in a second half-stripe no sourceregion is provided. FIG. 28 is a cross-sectional view taken along lineXVIII-XVIII of FIG. 27. As illustrated in FIG. 28 and as discussed abovewith the arrangement of FIG. 23-25, it is possible with this embodimentto reduce the distance “d” between adjacent body stripes, because in theportions of the drain layer 2 between adjacent body stripes there is acurrent flux I coming from only source region. In addition, as discussedabove with respect to the fourth embodiment, an advantage of thisembodiment is an increased ruggedness of the MOS-gated power device,because the body stripe 3 and the source region 62 are contacted by thesource metal layer along the entire length. It is to be appreciated thatalthough FIGS. 27-28 illustrate this embodiment as having the shape asshown in FIGS. 3a and 4 a, the body regions can also have the“bowl-like” body region shape as illustrated in Figs, 3 b and 4 b.

[0101]FIG. 29 is a top-plan view showing the layout and the reciprocalalignment of the photolithographic masks used to form the structure ofFIGS. 27-28. The same reference numerals as used in FIGS. 5, 18, 22 and26 have been used to illustrate the masks in FIG. 29. This embodiment ofthe invention can be fabricated with the same manufacturing processpreviously described. The only difference is the layout of the sourcemask, which results in the pattern of photoresist 15 shown in FIG. 29.As discussed above with respect to the fourth embodiment, for thisembodiment the distance “e” between adjacent elongated openings in thepassivation and polysilicon layers 9 and 8, and the dimension Lp of theelongated openings 12 should be at least twice the alignment toleranceLt of the photolithographic apparatus in use, to prevent layout errorsdue to the alignment errors between the source mask and the mask fordefining the elongated openings 12.

[0102] In summary, the embodiments illustrated in FIGS. 23-25 and 27-28are better from the point of view of the ruggedness of the MOS-gatedpower device, but are more critical than the first three embodimentsfrom the point of view of the alignment of the source mask with the maskfor defining the elongated openings 12 in the passivation layer 9. Inparticular, for the fourth and fifth embodiments the source mask shouldbe aligned within the dimension Lp of the elongated opening 12. Thismeans that the dimension Lp should be sufficient to provide forsimultaneous contact to two different regions. In other words, thedimension Lp should be larger than twice the alignment tolerance Lt ofthe photolithographic apparatus. However, as already mentioned, therequirement of this alignment between the masks does not prevent theobjective of shrinking the dimension Lp of the elongated opening 12 tothe optical resolution limit of the photolithographic apparatus, sincethe alignment tolerance Lt is always significantly smaller than theoptical resolution limit.

[0103] Having thus described several particular embodiments of theinvention, various alterations, modifications, and improvements willreadily occur to those skilled in the art. Such alterations,modifications, and improvements are intended to be part of thisdisclosure, and are intended to be within the spirit and scope of theinvention. Accordingly, the foregoing description is by way of exampleonly and is limited only as defined in the following claims and theequivalents thereto.

What is claimed is:
 1. A MOS technology power device comprising: asemiconductor material layer of a first conductivity type; a firstinsulating material layer above the semiconductor material layer; aconductive material layer disposed above the first insulating materiallayer; a plurality of elementary functional units, each elementaryfunctional unit including: an elongated body region of a secondconductivity type formed in the semiconductor material layer; a firstelongated window in the first insulating material layer and theconductive material layer above the elongated body region; a sourceregion of the first conductivity type, disposed in the elongated bodyregion along a length of the elongated body region; a second insulatingmaterial layer disposed above the conductive material layer and at eachvertical edge of the first elongated window, having a second elongatedwindow disposed therein; a metal layer disposed above the secondinsulating material layer, contacting a body portion of the body regionwherein no dopant of the first conductivity type is provided and thesource region through the second elongated window along the length ofthe elongated body region.
 2. The MOS technology power device accordingto claim 1 , wherein the first insulating material layer is an oxidelayer, the conductive material layer is a polysilicon layer, and thesecond insulating material layer is a passivation layer.
 3. The MOStechnology power device according to claim 2 , wherein the polysiliconlayer is doped with a dopant so as to have a low resistivity.
 4. The MOStechnology power device according to claim 2 , further comprising asilicide layer interposed between the polysilicon layer and thepassivation layer.
 5. The MOS technology power device according to claim4 , wherein the silicide layer is a cobalt silicide layer.
 6. The MOStechnology power device according to claim 1 , wherein each elongatedbody region includes a central heavily doped elongated deep body regionand two lateral lightly doped elongated channel regions, the centralheavily doped elongated deep body region having elongated edgessubstantially aligned with elongated edges of the first elongatedwindow.
 7. The MOS technology power device according to claim 1 ,wherein each source region includes a plurality of source portions ofthe first conductivity type extending in a longitudinal direction of theelongated body region and intercalated in the longitudinal direction ofthe elongated body region with body portions of the elongated bodyregion wherein no dopants of the first conductivity type are provided.8. The MOS technology power device according to claim 7 , wherein alength of the source portions is greater than a length of the bodyportions.
 9. The MOS technology power device according to claim 8 ,wherein the source portions and the body portions of the elongated bodyregion are substantially aligned in a direction transverse to thelongitudinal direction of the elongated body region, respectively withthe source portions and the body portions in body regions of adjacentelementary functional units.
 10. The MOS technology power deviceaccording to claim 8 , wherein the source portions and the body portionsof the body region are substantially shifted in the longitudinaldirection with respect to the source portions and the body portions inbody regions of adjacent elementary functional units.
 11. The MOStechnology power device according to claim 7 , wherein a length of thesource portions is substantially equal to a length of the body portions.12. The MOS technology power device according to claim 11 , wherein thesource portions and the body portions of the elongated body region aresubstantially aligned in a direction transverse to the longitudinaldirection, respectively, with the body portions and the source portionsof elongated body regions in adjacent elementary functional units. 13.The MOS technology power device according to claim 1 , wherein theelongated body region comprises a first longitudinal half-stripe and asecond longitudinal half-stripe merged together along a longitudinaledge of the first longitudinal half-stripe and the second longitudinalhalf-stripe, each half-stripe including a plurality of source portionsof the first conductivity type intercalated in the longitudinaldirection of each half-stripe with body portions of the half-stripewherein no dopants of the first conductivity type are provided, thesource portions and the body portions of the first longitudinalhalf-stripe being respectively aligned in a direction transverse to thelongitudinal direction, respectively, with the body portions and thesource portions of the second longitudinal half-stripe.
 14. The MOStechnology power device according to claim 13 , wherein the sourceportions in each half stripe are substantially aligned in the transversedirection with the source regions in each corresponding half-stripe ofthe body stripes of adjacent elementary functional units.
 15. The MOStechnology power device according to claim 1 , wherein the elongatedbody region includes a first longitudinal half-stripe and a secondlongitudinal half-stripe merged together along a longitudinal edge ofthe first longitudinal half-stripe and the second longitudinalhalf-stripe, the first longitudinal half-stripe including an elongatedsource portion of the first conductivity type extending in alongitudinal direction of the elongated body region for substantially anentire length of the elongated body region and the second longitudinalhalf-stripe extending in the longitudinal direction for substantiallythe entire length of the elongated body region and having no dopants ofthe first conductivity type.
 16. The MOS technology power deviceaccording to claim 1 , wherein the semiconductor material layer issuperimposed over a semiconductor material substrate.
 17. The MOStechnology power device according to claim 16 , wherein thesemiconductor material layer is lightly doped, and the semiconductormaterial substrate is heavily doped.
 18. The MOS technology power deviceaccording to claim 17 , wherein the semiconductor material substrate isof the first conductivity type.
 19. The MOS technology power deviceaccording to claim 17 , wherein the semiconductor material substrate isof the second conductivity type.
 20. The MOS technology power deviceaccording to claim 1 , wherein the first conductivity type is N-type,and the second conductivity type is P-type.
 21. The MOS technology powerdevice according to claim 1 , wherein the first conductivity type isP-type, and the second conductivity type is N-type.
 22. A process formanufacturing a MOS technology power device, comprising the steps of:forming a first insulating material layer over a semiconductor materialof a first conductivity type; forming a first conductive material layerover the first insulating material layer; selectively removing the firstconductive material layer to open at least one first elongated windowtherein, the first elongated window having elongated edges; forming abody region of a second conductivity type in the semiconductor materiallayer under the elongated window; forming a source region of the firstconductivity type in the body region along a length of the body regionso as to provide a body portion of the body region wherein no dopants ofthe first conductivity type are provided; forming a second insulatingmaterial layer above the first conductive material layer and along thelongitudinal edges of the first elongated window; forming a secondelongated window in the second insulating material layer; and forming asecond conductive material layer over the second insulating materiallayer, the second conductive material layer contacting the source regionand the body portion through the second elongated window along thelength of the body region.
 23. The process according to claim 22 ,wherein the step of forming the body region includes introducing adopant of the second conductivity type into the semiconductor materialthrough the first elongated window while using the first conductivematerial layer as a mask.
 24. The process according to claim 23 ,wherein the step of forming the body region includes implanting thedopant of the second conductivity type at a prescribed high energy andin a heavy dose, the high energy being sufficient to locate a peakconcentration of the dopant of the second conductivity type at aprescribed distance from a surface of the semiconductor material; andthermally diffusing the dopant of the second conductivity in thesemiconductor material type so that the body region comprises a centralheavily doped elongated deep body region and two lateral lightly dopedelongated channel regions, wherein elongated edges of the elongated deepbody region are substantially aligned with the longitudinal edges of thefirst elongated window.
 25. The process according to claim 22 , whereinthe step of forming the body region includes: implanting a first dopantof the second conductivity type into the semiconductor material throughthe first elongated window using the first conductive material layer asa mask, with a first implant energy suitable to locate a peak dopantconcentration of the first dopant substantially at a surface of thesemiconductor material layer; implanting a second dopant of the secondconductivity type into the semiconductor material layer through thefirst elongated window using the first conductive material layer as amask, with a second implant dose substantially higher than that of adose of the first implant, a second implant energy being suitable tolocate a peak dopant concentration of the second dopant at a prescribeddistance from the surface of the semiconductor material layer; andthermally diffusing the first dopant and the second dopant in thesemiconductor material so that the body region comprises a centralheavily doped elongated deep body region and two lateral lightly dopedelongated channel regions, wherein elongated edges of the centralheavily doped deep body region are substantially aligned with thelongitudinal edges of the first elongated window.
 26. The processaccording to claim 22 , wherein the first insulating material layer is asilicon dioxide layer, the first conductive material layer is a dopedpolysilicon layer, and the second insulating material layer is apassivation layer.
 27. The process according to claim 22 , wherein thestep of selectively removing the first conductive material layer to formthe first elongated window includes forming the elongated window havinga width substantially equal to an optical resolution limit of aphotolithographic apparatus used to selectively remove the firstconductive material layer.
 28. The process according to claim 22 ,wherein the first conductive material layer comprises a dopedpolysilicon layer and a silicide layer.
 29. The process according toclaim 28 , wherein the silicide layer is a cobalt silicide layer. 30.The process according to claim 22 , wherein the step of opening thefirst elongated window includes opening a plurality of the elongatedwindows substantially in parallel with one another, and wherein the stepof forming the body region includes forming a plurality of body regionsof the second conductivity type in the semiconductor material under theplurality of first elongated windows.
 31. The process according to claim22 , wherein the semiconductor material is a lightly doped layerepitaxially grown over a heavily doped semiconductor substrate.
 32. Themanufacturing process according to claim 31 , wherein the semiconductorsubstrate is of the first conductivity type.
 33. The manufacturingprocess according to claim 31 , wherein the semiconductor substrate isof the second conductivity type.
 34. The process according to claim 22 ,wherein the first conductivity type is N-type, and the secondconductivity type is P-type.
 35. The process according to claim 22 ,wherein the first conductivity type is P type, and the secondconductivity type is N-type.
 36. A MOS-gated apparatus, comprising: asemiconductor material of a first conductivity type; a plurality of bodyregions of a second conductivity type formed in a surface of thesemiconductor material, each body region having body portion wherein nodopants of the first conductivity exist; a source region of the firstconductivity type formed in a surface of each body region along a lengthof each body region; a first insulating material layer disposed abovethe surface of the semiconductor material; a conductive layer disposedabove the first insulating material layer; a plurality of firstelongated windows in the conductive material layer, each elongatedwindow in the conductive material layer exposing a respective sourceregion and a respective body region; a second insulating material layerdisposed above the conductive material layer and at each elongated edgeof the first elongated window, having a plurality of second elongatedwindows disposed therein; and a metal layer disposed above the secondinsulating material layer and contacting each body portion and each ofsource region along the length of each body region through the pluralityof second elongated windows.
 37. The MOS-gated apparatus as claimed inclaim 36 , further comprising a silicide layer disposed above theconductive material layer and beneath the second insulating materiallayer.
 38. The MOS-gated apparatus as claimed in claim 36 , wherein eachbody region is an elongated body region and includes a central heavilydoped elongated deep body portion in which the respective source regionis disposed and lateral lightly doped elongated regions disposed atlateral edges of the elongated body region and underneath the conductivematerial layer, the lateral lightly doped elongated regions forming achannel region of the MOS-gated apparatus.
 39. The MOS-gated apparatusas claimed in claim 36 , wherein the body region is an elongated bodyregion and each source region includes a plurality of source portionsdisposed along the length of the respective elongated body region whichare intercalated with body portions of the respective elongated bodyregion.
 40. The MOS-gated apparatus claimed in claim 39 , wherein eachsource portion has a first length and each body portion has a secondlength, and wherein the first length of each source portion is greaterthan the second length of each body portion.
 41. The MOS-gated apparatusas claimed in claim 40 , wherein each source portion in one body regionis substantially aligned in a direction transverse to the length of thebody region with a respective source portion in each adjacent bodyregion, and wherein each body portion within the body region issubstantially aligned in the transverse direction with a respective bodyportion in each adjacent body region.
 42. The MOS-gated apparatus asclaimed in claim 40 , wherein each source portion in one body region isshifted in a longitudinal direction of the body region with respect to arespective source region within each adjacent body region, and whereineach body portion within the body region is shifted in the longitudinaldirection with respect to a respective body portion in each adjacentbody region.
 43. The MOS-gated apparatus as claimed in claim 39 ,wherein each source portion has a first length and each body portion hasa second length, and wherein the first length is substantially equal tothe second length.
 44. The MOS-gated apparatus as claimed in claim 43 ,wherein each source portion in one body region is substantially alignedin a transverse direction to the length of the body region with arespective body portion in each adjacent body region.
 45. The MOS-gatedapparatus as claimed in claim 36 , wherein each body region is anelongated region, wherein the elongated body region includes a firstelongated stripe and a second elongated stripe that are merged togetheralong an elongated edge of each of the first elongated stripe and thesecond elongated stripe, each of the first elongated stripe and thesecond elongated stripe including a plurality of source portions and aplurality of body portions extending in a longitudinal direction of thefirst elongated stripe and the second elongated stripe, each sourceportion of the first elongated stripe being substantially aligned in adirection transverse to the longitudinal direction with each bodyportion of the second elongated stripe, and each body portion of thefirst elongated stripe being substantially aligned in the transversedirection with each source portion of the second elongated stripe. 46.The MOS-gated apparatus as claimed in claim 36 , wherein each bodyregion is an elongated region having a longitudinal direction andwherein each source region is an elongated region disposed in theelongated body region for substantially an entire length of theelongated body region.
 47. A process for forming a MOS-gated apparatuscomprising the steps of: providing a semiconductor substrate including asemiconductor material layer of a first conductivity type disposed overa highly doped semiconductor substrate; forming a first insulatingmaterial layer above the semiconductor material layer and a conductivematerial layer above the first insulating material layer; selectivelyremoving the conductive material layer to provide a plurality of firstelongated windows in the conductive material layer and exposing thesemiconductor material layer beneath each first elongated window;forming a respective body region of a second conductivity type in thesurface of the semiconductor material layer through the respective firstelongated window in the conductive material layer; forming a sourceregion of the first conductivity type in each body region along a lengthof the body region so as to provide a body portion of the body regionwherein no dopants of the first conductivity type exist; forming asecond insulating material layer above the conductive material layer andalong the longitudinal edges of each first elongated window; forming aplurality of second elongated windows in the second insulating materiallayer; and forming a metal layer above the second insulating materiallayer and contacting each body portion and each source region along thelength of the body region through each second elongated window in thesecond insulating material layer.
 48. The process for forming theMOS-gated apparatus as claimed in claim 47 , wherein the step of formingthe source region includes the steps of: depositing a photoresist layerover the surface of the semiconductor substrate; selectively exposingthe semiconductor substrate to an energy source through aphotolithographic mask; selectively removing the photoresist layer fromthe surface of the semiconductor substrate to form windows in thephotoresist layer; and implanting dopants of the first conductivity typethrough the first elongated windows in the conductive material layer andthrough the windows in the photoresist layer to form the source regionwithin each body region.
 49. The process for forming the MOS-gatedapparatus as claimed in claim 48 , wherein the step of forming the bodyregion includes forming an elongated body region and wherein the step offorming the source region includes forming a plurality of sourceportions in each elongated body region, the plurality of source portionsbeing intercalated with a plurality of body portions of each elongatedbody region along the length of each elongated body region.
 50. Theprocess for forming the MOS-gated apparatus as claimed in claim 49 ,wherein the step of forming the source region further includes formingeach source portion with a first length and forming each body portionwith a second length, wherein the first length is greater than thesecond length.
 51. The process for forming the MOS-gated apparatus asclaimed in claim 50 , wherein the step of forming the source regionfurther includes forming each source portion within one elongated bodyregion such that the source portion is substantially aligned in adirection transverse to the length of the elongated body region with arespective source portion in each adjacent elongated body region, andforming each body portion within the one elongated body region such thateach body portion is substantially aligned in the transverse directionwith a respective body portion in each adjacent elongated body region.52. The process for forming the MOS-gated apparatus as claimed in claim50 , wherein the step of forming the source region further includesforming each source region within one elongated body region so that itis shifted in the elongated direction of the body region with respect toa respective source portion in each adjacent elongated body region, andforming each body portion within the one elongated body region such thateach body portion is shifted in the elongated direction with respect toa respective body portion in the each adjacent elongated body region.53. The process for forming the MOS-gated apparatus as claimed in claim49 , wherein the step of forming the source region further includesforming each source portion with a first length and forming each bodyportion with a second length, wherein the first length is substantiallyequal to the second length.
 54. The process for forming the MOS-gatedapparatus as claimed in claim 53 , wherein the step of forming thesource region further includes forming each source region within oneelongated body region so that each source region is substantiallyaligned in a direction transverse to a length of the elongated bodyregion with a respective body portion in each adjacent elongated bodyregion, and forming each body portion within the one elongated bodyregion such that each body potion is substantially aligned in thetransverse direction with a respective source portion within eachadjacent elongated body region.
 55. The process of forming the MOS-gatedapparatus as claimed in claim 48 , wherein the step of forming each bodyregion includes forming an elongated body region in the semiconductormaterial layer, and wherein the step of forming a source region in eachbody region includes the steps of: forming a first elongated stripehaving a longitudinal dimension, including a plurality of sourceportions intercalated with a plurality of body portions along thelongitudinal dimension for substantially an entire length of theelongated body region; and forming a second elongated stripe having alongitudinal dimension and a longitudinal edge that is merged with alongitudinal edge of the first elongated stripe, and including aplurality of body portions that are intercalated with a plurality ofsource portions along the longitudinal dimension such that each sourceportion of the first elongated stripe is substantially aligned in adirection transverse to the longitudinal dimension with a respectivebody portion of the second elongated stripe and such that each bodyportion of the first elongated stripe is substantially aligned in thetransverse direction with a respective source portion of the secondelongated stripe.
 56. The process for forming the MOS-gated apparatus asclaimed in claim 48 , wherein the step of forming the body regionincludes forming an elongated body region and wherein the step offorming the source region includes forming an elongated source regionfor substantially an entire length of the elongated body region.
 57. Theprocess for forming the MOS-gated apparatus as claimed in claim 47 ,wherein the step of forming the body region includes selectivelyintroducing a dopant of the second conductivity type into thesemiconductor material layer through each first elongated window whileusing the conductive material layer as a mask.
 58. The process forforming the MOS-gated apparatus as claimed in claim 57 , wherein thestep of forming the body region includes forming an elongated bodyregion by implanting the dopant of the second conductivity type at aprescribed high energy and in a heavy dose, the high energy beingsufficient to locate a peak concentration of the dopant of the secondconductivity at a prescribed distance from the surface of thesemiconductor material layer; and thermally diffusing the implanteddopant of the second conductivity type so that the body region comprisesa central heavily doped deep body region and two lateral lightly dopedchannel regions, the central heavily doped deep body region havingelongated edges substantially aligned with longitudinal edges of thefirst elongated window.
 59. The process for forming the MOS-gatedapparatus according to claim 47 , wherein the step of forming the bodyregion includes forming an elongated body region by the steps of:implanting a first dopant of the second conductivity type into thesemiconductor material layer through each first elongated window usingthe conductive material layer as a mask, with a first implant energysuitable to locate a peak dopant concentration of the first dopantsubstantially at a surface of the semiconductor material layer;implanting a second dopant of the second conductivity type into thesemiconductor material layer through each first elongated window usingthe conductive material layer as a mask, with a second implant dosesubstantially higher than that of a dose of the first implant, a secondimplant energy being suitable to locate a peak dopant concentration ofthe second dopant at a prescribed distance from the surface of thesemiconductor material layer; and thermally diffusing the dopant of thesecond conductivity in the semiconductor material so that the bodyregion comprises a central heavily doped elongated deep body region andtwo lateral lightly doped elongated channel regions, wherein elongatededges of the elongated deep body region are substantially aligned withthe longitudinal edges of the first elongated window.